S6. Electropackage System and Interconnect Product

Room 317, COEX Thursday, January 24
1:00pm to 5:20pm

Packaging Growth through Technology Diversification
Thanks to the semiconductor’s evolution, electronics markets are significantly expanded from the mainframe computing era to the mobile computing era. Today it is facing the 4th industry generation requires intelligence network in addition to performance excellence. For supporting this, every semiconductors area’s involvement, Design-Chip-Packaging-Test, is needed. Especially packaging technology’s flexibility and confrontation-ability will play a particularly important role with packaging as an Advanced-FOWLP using 3D IC and 2.5D IC, MEMS/Sensor, SIP, vertical integration package, and mature package’s advancing. It is challengeable. But this session will be helpful for understanding the new advanced packaging technologies.
  • Date: Jan 24(Thu),2019
  • Time: 13:00-17:20
  • Room: #317, Conference Room (South), COEX
  • Language: English (Simultaneous interpretation will NOT be provided​​)



  • Gu Sung Kim (Kangnam University)
  • Young Bae Park (Andong National University)
  • Min Suk Suh (SK hynix)
  • WS Shin (ASE Korea)
  • Seh Kwang Lee (Ehwa Diamond)
  • Hanchoon Lee (DB HiTek)
  • Ji Young Chung (Amkor Technology Korea)
  • Soon Jin Cho (Samsung Electro-Mechanics)
  • Taeje Cho (Samsung Electro-Mechanics)
  • Hwail Jin (Samsung Electronics)
  • HR Han (ASE Korea)


Registration Fee

  SEMI Member Non-Member Student
Early Bird (by Jan 16) 150,000 won 180,000 won 80,000 won
Onsite 180,000 won 200,000 won 100,000 won



High-Speed Serdes Package Development for Artificial Intelligence (AI) Applications
The Growth of Heterogeneous Integration; Enabling Technologies and Materials
*The agenda will be subject to change without notice.
Sponsored by: 
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